The EM performance, however, could not be improved as the dimensions of Cu lines decrease. Copper has lower electrical resistance and superior resistance to electromigration compared to aluminum and is in the process of replacing aluminum as the interconnect metal for the next generation of integrated circuits. This RC delay is the product of the dielectric capacitance (C) and the conductor resistance (R), which can be calculated according to Eqs. Currently, although Cu metallization has been successfully integrated into ICs, a different and complex process to fabricate Cu interconnects has many remaining issues, resulting in integration and reliability challenges. Use of heavy metals, such as Fe (iron) and Ni (nickel), and alkali metals, such as Na (sodium), is avoided, and in particular, Cu (copper), when a Si (silicon) substrate is being used (Fig. Clearly, with full-coverage Cu deposition, post-deposition wafers have a Cu film across the front side of the wafer that extends onto the beveled edge and even onto the wafer backside (Fig. This is particularly true for non-DRAM fabs. Sept. 2015-Mai 20204 Jahre 9 Monate. These problems can be solved through: (i) reducing the down-force during Cu CMP process; (ii) improving the adhesion between layers in the interconnect; (iii) optimizing the used slurry; (iv) depositing a relatively dense material, such as SiO2 or nonporous SiCOH films on the top of the porous low-k dielectric film; and (v) performing an optimized wetting clean after the CMP process [70, 71, 72]. To minimize the damage on the porous low-k material, low-k material optimization and resist strip condition are chosen, and the process integration modification has been provided. Therefore, the short wires that have a length below a critical threshold length (typically on the order of 550m), the back flux of atoms prevents killer voids from forming, and the wires are immortal. Figure6 plots the maximum required current density at 105C for Cu lines. This reduction is amplified with decreasing the dielectric constant of low-k dielectrics. If gold could diffuse into the quartz tubes, it could also continue on and contaminate the heating coils. This work at Sematech recognized the lack of methods for detecting Cu on the beveled edge and backside of production wafers. Tata has already announced a partnership with Tokyo-based Renesas Electronics in June this year, noted the report, which is based around semiconductor design and development. 3. Separate gowning, gloves, maintenance tools, pods, and cassettes need to be introduced for non-copper and copper areas. Deposition and dry etching contribute to contamination of the wafer backside and at the edge. }, abstractNote = {Particulate contamination is an important problem in semiconductor device manufacturing. These copper deposition processes can result in a process-induced copper contamination via an uncovered barrier layer. It does not store any personal data. The latter two materials (carbon nanotube and collective excitations) can provide a different conductance mechanism, but they are still in the research and development phase. An FIB with an acceleration voltage of 30 kV creates a damage layer of nearly 30 nm on silicon. The microstructure of Cu interconnects also plays an important role in EM performance. Nanoparticle-Catalyzed Growth of Semiconductor Nanowires. First, metrology tools are not available to measure backside contamination without wafer handling, putting the device side at risk. The test structure of stress-induced void is simple via-chain structures. Analytical cookies are used to understand how visitors interact with the website. J-C. Lin, C. Lee, A Study on the Grain Boundary Diffusion of Copper in Tantalum Nitride Thin Films, ECS and Solid-State Letters, pp. In the absence of internal gettering, trace amounts of copper can migrate to the backside from the front side of the silicon wafer contaminated by copper. A thermocouple is composed of two dissimilar metal and/or semiconductor wires joined together. Hence, to remove Cu oxides and avoid Cu re-oxidation, an in situ clean is required. In order to obtain the coefficients of the most probable chemical reaction for copper plating, the ratio between the numbers of consumed silicon atoms (n Si) 30, p. 1, 1983. These studies are of great importance in semiconductor Most contamination issues in the fabrication of submicron devices come from metallic contaminants. The primary objective of this strategy is the development of a plan that will ensure the safe introduction and operation of copper in the cleanroom or fabrication facility. Current Cu deposition methodologies do not ensure that the Cu film will only be deposited in the device region of the wafer. The obtained results were contradictory [93, 94, 95] since some authors reported H2-based plasma clean is better. There's just one problem - the seam is within the site of Southern Copper Corp's planned $2.6 billion Los Chancas mine. Furthermore, if this self-forming barrier process is controlled precisely, there is no barrier at the via bottom connecting the underlying metal line because of high diffusivity of Mn in Cu [47, 48]. Failure rate of stress-induced void versus M2 line width and V2 via size after annealing stress at 225C for 1000h. Reproduced with permission from Ref. Discretionary Wiring A technique which permits the selective interconnection of only good cells on the chip, bypassing the defective units. (SPCE is also applicable to removing sacrificial oxide, nitride, or other films.). Melting point and resistivity of different metals. The material on this site may not be reproduced, distributed, transmitted, cached or otherwise used, except with the prior written permission of WTWH Media Privacy Policy | Advertising | About Us, Enclosures isolate robotic and lab automation processes and equipment, Safely contain airborne particulate with CCS (Controlled Containment System), Modular cleanlabs feature modular construction, Enclosures for Lab Automation and Robotics. At Sematech, recent cooperation between SEZ and major suppliers of Cu deposition equipment has focused on the testing and optimization of Spin-Process contamination elimination (SPCE), a proprietary technology of the SEZ Group. part of the Developments in Surface Contamination and Cleaning series provide a state-of-the-art guide In order to minimize the Blech effect on EM results, the length of the tested Cu line must be sufficiently long. We performed additional testing of the SPCE process to quantify the effectiveness of removing Cu deposited over an oxide film. A base line for copper contamination levels for the copper, non-copper, and shared tools is important for control of cross-contamination. The biggest challenge for Cu sputtering process is to achieve good step coverage in the high aspect ratio via and trench. As an electric current is applied on a metal lead, the momentum transfer is occurred from the electrons to the metallic atoms, resulting in the migration of the metallic atoms. Transim powers many of the tools engineers use every day on manufacturers' websites and can develop solutions for any company. The minimum feature size has advanced from 10m down to 10nm, the cost per transistor has decreased by seven orders of magnitude, and the maximum number of transistors per chip has increased by at least 10 orders of magnitude [1]. Therefore, the approaches to optimize Cu interfaces applied for EM improvement also provide great help for stress-induced void [129, 130, 131]. Such a plan can, however, produce scrap and be costly for the long term. A high tensile stress in the metal at the edge of the via and a weak adhesion between the barrier metal and the underlying Cu at the bottom of the via are responsible for this failure mode. This fact amazed the production people, but anyone who has worked on semiconductor processes knows that you can never just look at the usual suspects. In semiconductor device manufacturing, contamination caused by metal impurities has a large impact on decreases in device reliability. For metal contamination in solution, there are two alternative reaction pathways that Phys. This option allows users to search by Publication, Volume and Page. Programs need to be developed to manage the supplier-supplied spare parts which might have been exposed to copper. We tested the exclusion zone with EDS. By Hank Hogan. Such isolation might be total separation or partial area separation. A method of removing copper contamination from a semiconductor wafer, comprising the following steps. Typically, there are three main steps in Cu CMP process [64]. The wafer backside has long been a troublesome, ignored source of yield loss. Data in Fig. P. Lysaght et al., A Novel Wafer Backside Spin-Process Contamination Elimination for Advanced Copper Device Applications, ECS, October 1999. The typical leakage current versus the stress time is the initial decrease in leakage current due to trapping of charge, followed by stress-induced leakage current, and finally breakdown [150]. Sometimes, a sandwich dielectric stack film (SiCOH/Si(C)N/SiCOH) is used in order to control the depths of the via and metal precisely. The first factor that increases the resistivity of the metal line is grain boundary scattering. Soc., Vol. Selecting this option will search the current publication in context. The CV plots once again confirmed the presence of heavy metal. Failure to achieve the condition depicted in Fig. The usual suspects in this case are positive ions (sodium) or heavy-metal contamination causing leakage in the oxide layers. Contact our London head office or media team here. Electrical parameters such as the threshold voltage (VT0), the drain . Table3 lists the properties of Cu films obtained by different deposition technologies. This leads to a larger RC delay in the advanced technology nodes, which surpasses the gate delay and becomes a limiting factor in ICs performance [3, 4, 5, 6]. The qualified supplier should be able to develop plans for preventing cross-contamination based on physical handling and storage of copper and non-copper materials; procedures and training of personnel; systems for tracking with advanced software systems; technical resources and expertise for contamination evaluation. The EM-induced void will form under the via (early failure) and in the wire far from the via (late failure). In Cu interconnects, interface diffusion has the lowest activation energy, presenting the major path for EM. The main purpose of continuous scaling of the device dimensions is to improve the performance of the semiconductor microprocessors and to pack more devices in the same area. Thus, no further EM lifetime improvement is observed at the operation frequencies above this point [88]. Traditional methods (i.e., wet benches, spray processors, and scrubbers) are not friendly to front-side Cu. During a prolonged stress at high electric fields, electric damage can occur in dielectric materials. The operation timing is after Cu plating and before Cu CMP step. Control of etchant viscosity, simultaneous radial and tangential etchant flows, and Bernoulli gas flow enables etching of Cu contamination from a wafer backside, and a wraparound effect that removes thin-film contamination from the beveled edge and front-side exclusion zone (0.5-5.0mm). Two mechanisms can explain this unique behavior. Keywords Aggregated transfer factor (T ag Finally, short conclusion and future trend for conductors used in the BEOL interconnects are provided in Section 6. The level of copper on the freshly cleaned wafer surface is measured to be close to 1.0 E+10 atoms/sq cm. Therefore, for these new conductor materials to successfully integrate into the semiconductor industry is a long way off. The transistors inside the new quartz tubes were good ones and met all the specifications. 3 show that EDS counts for Cu dropped from the thousands to 30 at 5mm from the edge in the exclusion zone and to below the detection level near the edge of the wafer. It is important to develop protocols for monitoring trace amounts of copper introduced onto silicon wafers by the processing tools. The interface between Cu line and the capping layer is the dominating EM transport path for Cu damascene interconnects due to the lowest activation energy for diffusion [83]. 139, p. 3317, 1992. Relative diffusivity of copper compared to other metals, at 700C, is shown in Figure 1. This also includes contact with copper contaminated tools or materials used in processing copper wafers coming in contact with wafers or materials used in FEOL applications. By this approach, the stress gradient is reduced and the volume of the killer void is increased, thus enhancing stress-induced void. Prevention of Copper Cross-Contamination on Cu Process and Non-Cu Process Mixed Fabrication Abstract: When the integration of Cu process and non-Cu process is mixed in the fabrication, the prevention of Cu cross-contamination between wafer-to-wafer and machine-to-machine is critical. The semiconductor device further comprises a copper-containing metal layer and a diffusion barrier layer arranged between the substrate and the buried insulating layer, wherein a composition. Clip, share and download with the leading R& magazine today. The layout for such interconnection paths is generally computer programmed and generated. BEOL tools that generate copper, copper particulate, or ones used in copper processing steps and have potential for spreading copper from the backside or bevel, can be considered high-risk. Very large scale integrated circuit (VLSI) devices such as the current generation of 16 megabit DRAM (dynamic random access memory) have . However, in order to successfully deposit Cu film during ECP process, a Cu seed layer is needed. Cu dishing and oxide erosion as shown in Figure4 are the main problems associated with Cu CMP process [65, 66, 67]. Menu. Browse the most current issue of R&D World and back issues in an easy to use high quality format. The material is exposed to an aqueous solution comprising about 4% to about 30% of at least one acid and at least one surfactant. Replacing these tubes upset the production-team members, but they felt that they had at least cured the contamination problem. It is postulated that the accelerated electrons, injected from the cathode, transport inside low-k dielectric by means of Schottky-Emission or Poole-Frenkel conduction. Furthermore, a baseline for copper contamination from the shared tools can be established and appropriate action plans developed to prevent contamination. Yields were decreasing on a daily basis because of high leakage failures. While working in the 1980s for a major semiconductor manufacturer, we had a major yield problem that was baffling the production team. Discovered resist chemical contamination issue that saved Intel from running discrepant material and saved the company 300K. These methods can detect parts per trillion of copper and other metals. Spinetch is a registered trademark of Merck Corp. Patrick S. Lysaght received his BSEE from the University of New Mexico and has 16 years of research experience at Los Alamos National Laboratory. Moreover, in Cu damascene lines with bamboo-like grain structure (i.e., no grain boundary diffusion), the activation energies for diffusion were 1.0eV for an SiN or SiCN capping layer, 1.4eV for an Ta/TaN capping layer, and 2.4eV for a CoWP capping layer [99]. Finally, an electrical breakdown occurs as a conducting path is formed. Nickel alloys with: b.1.a. This can result in further process contamination with copper. In Al and Cu interconnects, the activation energies for diffusion in different diffusion paths are different. Semiconductor Providing filtration, purification and separations solutions for a broad range of fluids, such as chemicals, gas, water, CMP slurries and photoresist. CMP processes can only remove copper from the face of the wafer, leaving any film or contamination on the beveled edge free to migrate during subsequent operations. Metal nitride barrier layers are designed to prevent migration of copper within the die. In order to mitigate and continue providing value to our customers, Cirtek has developed copper wire bonding technology since 2008. As the concentration of Cu in the dielectric reaches a critical value, the dielectric breakdown event occurs. In this chapter, the deposition method of Cu films and the interconnect fabrication with Cu metallization are introduced. - Surface structuring in the micro- and nanometer regime for functionalization (wettability . In the presence of copper contamination carrier generation is dominated by surface generation . For this reason, Cu film must be surrounded by a good diffusion barrier layer. Ar sputtering clean to physically remove Cu oxides is a typical physical method. Hence, H2 or NH3 is widely used reduction gas [60, 61, 62]. First, the diffused Cu atoms can catalyze the bond breakage reaction by inducing permanent bond displacement in the dielectric. A work cell approach provides process tools, metrology, and material handling tools to perform all process steps and support operations without leaving the area. Means for control and prevention of copper contamination are outlined above. Though various sources of contamination by copper exist, particular emphasis is placed on the prevention of contamination using the principle of segregation. 1 is predominant when concentrated (70%) nitric acid reacts with Cu [3]: Cu(s) + 4H+(aq) + 2NO3(aq)> (4) Cu2+(aq) + 2H2O(l) + 2NO2(g). The copper on the wafer surface is measured using total reflection X-ray fluorescence spectroscopy (TXRF). It had taken three months for the gold to diffuse from the outside to the inside of the tubes; it then began to ruin the wafers inside the tubes. The cookie is used to store the user consent for the cookies in the category "Analytics". Experiment and model results of electromigration lifetime scaling with the reduction of interconnect dimension. Necessary cookies are absolutely essential for the website to function properly. A semiconductor wafer having copper contamination thereon is provided. Overall, Cu contamination has been a challenge in the field of Si semiconductor devices. Overall prevention plans must include integration of the copper cleaning process following deposition and chemical mechanical planarization (CMP). To minimize Cu diffusion into the dielectric to avoid reliability degradation in TDDB, several process strategies have been proposed including using adequate metal barrier layers [167, 168], minimizing residues after post-CMP cleaning [169], and minimizing air exposure prior to capping of the Cu [150, 153]. Thus, the wider Cu lines take less time to form a killer void and have a weak resistance against stress-induced void. Interconnect dimensions with technology nodes. low-k damage). Determination of the dedicated tool should be based on risk-benefit analysis. To use a thermocouple, we place the junction in the test environment and keep the two ends outside test environment at a reference temperature. Selecting this option will search all publications across the Scitation platform, Selecting this option will search all publications for the Publisher/Society in context, The Journal of the Acoustical Society of America, Impact of copper contamination on the quality of silicon oxides, Siemens AG, Components Division, Semiconductor Technology, OttoHahnRing 6, 8000 Munich 83, Federal Republic of Germany, Siemens AG, Corporate Research Laboratories, OttoHahnRing 6, 8000 Munich 83, Federal Republic of Germany. A method and apparatus for reducing oxidation of an interface of a semiconductor device thereby improving adhesion of subsequently formed layers and/or devices is disclosed. Patrick S. Lysaght, Sematech Inc., Austin, TexasMichael West, SEZ America Inc., Phoenix, Arizona. Additionally, the use of metal capping layers [133] and/or Cu alloying lines [106, 107], which are used to improve EM has also shown to reduce the failure rate of stress-induced void. Semiconductor Manufacturing The semiconductor manufacturing cleanroom (commonly called the "fab" for fabrication facility) is a unique manufacturing environment characterized by perhaps the cleanest air found in any industry. Wafers partially contaminated by copper can be a source of contamination under some circumstances. Nevertheless, it is clear that both the H2 and NH3 plasma clean can enhance EM lifetime. Can wafer fabrication budgets afford the expenditure of millions of dollars on dedicated Cu production equipment? The measured failure times are usually plotted using a log-normal distribution and analyzed [23]. They all have their own idea of where and how they want Cu systems integrated and to what extent they will sacrifice flexibility. The extent to which the reduction of nitric acid takes place is a function of the concentration of the acid, the temperature at which the reaction is carried out, and the nature of the reducing agent. As PhD students, we found it difficult to access the research we needed, so we decided to create a new Open Access publisher that levels the playing field for scientists across the world. The time-dependent dielectric breakdown can occur in gate dielectrics and BEOL dielectrics [142, 143]. During CMP process, the wafers are placed face-down on a rotating pad on which the slurry is dispensed, resulting in the removal of the film by chemical reaction and mechanical force. The first step is Cu film removal, stopping on the barrier layer. A high tensile stress in the metal at the edge of the via was detected through stress simulation modeling [127, 128]. Additionally, in order to strengthen adhesion, a SiH4 exposure process is inserted between a plasma clean and a dielectric deposition processes to form a thin Cu silicide layer. This cookie is set by GDPR Cookie Consent plugin. 181-183, April 1999. Additional risks of such contamination also exist for non-copper BEOL processes. Theoretically, however, during chemical mechanical planarization (CMP), the exclusion zone would be free of Cu, but serious concerns remain for cross-contamination from the remaining Cu film on the beveled edge. The spectra were taken at 2.0 MeV under normal incidence of a 4He + beam and with a scattering angle of 165 o. Changing glassware was not permanently solving the problem. Cu film, barrier layer, and the dielectric are polished simultaneously. The integration of copper into semiconductor processing presents new opportunities - and challenges. experiences for your customers. Wafer and cassette carriers should be clearly identified and be cleaned to prevent copper material build-up. Applications of Gold Nanoparticles in Cancer Imagi Department of Electrical Engineering, National Chi-Nan University, Nan-Tou, Taiwan, ROC. Functional cookies help to perform certain functionalities like sharing the content of the website on social media platforms, collect feedbacks, and other third-party features. Copper (Cu) has been widely used as interconnect materials in semiconductor industry, due to its advantages of high electrical, thermal conductivities, good electro-migration resistance and low. Lysaght is a senior process engineer at Sematech Inc., 2706 Montopolis Dr., Austin, TX 78741; ph 512/356-3500, fax 512/356-3425, e-mail [emailprotected], Michael West received his BS in mechanical engineering from Rensselaer Polytechnic Institute and his MBA from the University of Texas, Dallas. Ext. After completing the metal deposition, Cu chemical mechanical polishing (CMP) process is used to remove the excess metal over the field regions. Showing that the beveled edge is clean after a process step is difficult, however, and testing methods lead to speculation on the quality of the results, because VPD data are highly dependent on the techniques used during the process. To improve plasma and chemical resistance on various vacuum components used for semiconductor manufacturing equipment, various ceramic coating techniques have been applied. Automation of the flow of materials can be used for segregation. By applying an electric current, Cu ion (Cu+2) is reduced to Cu, which deposit onto the seed layer. In order to fabricate Cu dual damascene interconnects, various process flows were developed. This would enable the semiconductor fab to determine the frequency of cleaning requirement and acceptability of the level of contamination. Materials such as tools and equipment exposed to the copper environment should be segregated from the rest of the non-copper wafer processing environment. Our team is growing all the time, so were always on the lookout for smart people who want to help us reshape the world of scientific publishing. Hence, the energy and time in the Ar sputtering clean process must be carefully controlled in order to alleviate these two phenomena. Materials exposed to copper must be identified to prevent accidental mix-up with non-copper parts. Activation energy for different diffusion paths for Al, Al/Cu, and Cu metal. SPCE is a single-wafer processing technology that dispenses a liquid chemical etchant onto the backside of a spinning wafer held front-side-down by a nitrogen cushion and centered with perimeter pins in a Bernoulli wafer chuck. That is, Cu film is patterned by etching process. If silicon is left exposed not covered by tantalum tantalum-nitride, silicon oxide, or another barrier film Cu readily diffuses into it. How? The main failure mode of stress-induced void is void formation under vias due to the stress gradient in the underlying Cu line and the presence of the via-metal interface [116]. In this theory, Cu could act as a precursor for an ultimate dielectric breakdown. The cookies is used to store the user consent for the cookies in the category "Necessary". This cookie is set by GDPR Cookie Consent plugin. It is the rarest naturally occurring element in the Earth's crust, occurring only as the decay product of various heavier elements. Aluminium Skived Heat Sinks Skived heat sinks are manufactured by peeling fins from a bar of solid copper or aluminum, using a sharp and Beliebt bei Jose Fonseca New Report Identifies Challenges to Continued U.S. Most of other metals like Copper,Nickel,silver etc will co deposit with gold and will get removed though the characteristic of the deposit will change. We place cookies on your device to give you the best user experience. To solve this issue, new material such as tungsten (W), silicides, carbon nanotube, or collective excitations could be an alternative to Cu as interconnects [42, 43]. Leadership in #Semiconductor Design, #Innovation (by SIA and BCG) Following the historic The so-called chain effect from a single contaminated tool to many other tools can be prevented only by proper development of an appropriate segregation strategy. Out of these, the cookies that are categorized as necessary are stored on your browser as they are essential for the working of basic functionalities of the website. In this step, removal selectivity is not considered because only Cu film is polished. The test structure for the TDDB reliability evaluation has two typical configurations: comb-comb or comb-serpentine layout [146, 147, 148, 149], as shown in Figure11. 1 and Fig. But many wafer fabs do not possess a complete set of tools dedicated exclusively to Cu-based, full-flow device processing. Then, in Section 3, the deposition methods of Cu metal are introduced and compared. Stand-alone systems provide flexibility, process capability, and desired yield to prevent losses caused by copper contamination of mixed system. Due to high diffusivity, surface contamination becomes evenly distributed with minimal thermal processing.4,5 Copper migrates quickly even at room temperature. Two typical EM test structures: downstream stressing and upstreaming stressing, as shown in Figure5. Specifically, Cu must be eliminated from a wafer's backside, beveled edge, and front-side edge-exclusion zone so that it is not transmitted to subsequent wafer fabrication operations. Research projects; Research infrastructure Generally, 2030 samples are tested for an EM test. Need for rework of copper wafers along with integration flexibility must be determined. One strategy for isolation is to designate individual bays or tools as only for copper use and allowing particular types of carriers designated for copper use only. Temporary isolation of copper materials for any process change or control of work in progress should be followed wherever necessary. Contamination concerns dull copper`s benefits. Traditionally, low concentrations of metals in plating solutions can be monitored using highly sensitive polarography methods or spectral methods such as AAS or ICP [1]. Among all metals in the world, three kinds of metal have lower resistivity than Al with a resistivity of 2.65 -cm: Gold (Au; 2.214 cm), copper (Cu; 1.678 cm), and silver (Ag: 1.587 cm). by a lithium-drifted silicon detector (Nuclear Semiconductor) with a resolution of about 200 eV, to predetermined times or particle counts, in 512 channels of . (A) Comb-comb structure. In other words, as the feature size of ICs is continuously scaling down, the speed of the device increases due to a shorter channel length, although, resistance-capacitance (RC) delay produced by the interconnects limits the chip speed. Copyright 2022 WTWH Media LLC. The reaction in Eqn. To sign up for alerts, please log in first. Gowning requirements for working in cleanroom chase areas are particularly important since particle generation in certain chases in proximity to copper tools can increase the risk of copper contamination. Moreover, from the perspective of stressing method, alternative current (AC) stressing can enlarge EM lifetime of Cu lines as compared to the conventional direct current stressing [88, 89]. In a downstream stressing test structure, electron flow is from metal-2 to metal-1 through Via-1. While a wafer backside and back edge can be hermetically sealed and protected from copper contamination during electroplating, the front-side exclusion zone and beveled edge are still vulnerable because clamping during electroplating is not a totally effective mask. As porous low-k dielectric films are used as the BEOL insulators to further reduce the capacitance between the metal lines, these two issues also become more severe. Processes and procedures must be developed to control such cross-contamination while also controlling cycle time and cost. It is difficult to achieve large grain size in narrow lines because grain growth of Cu in trenches is inhibited at small dimensions. The mechanism to remove Cu oxides in clean process can be achieved by either physical removal or chemical reaction [58]. The leakage current is measured with the stress time. Compared with these three metals, Cu has been recognized to be a candidate as a conductor in the BEOL interconnects for integration consideration. Noble and Precious Metals - Properties, Nanoscale Effects and Applications, Submitted: June 28th, 2017 Reviewed: November 13th, 2017 Published: January 26th, 2018, Edited by Mohindar Singh Seehra and Alan D. Bristow, Total Chapter Downloads on intechopen.com. The extent to which this is justifiable is explored via a thorough X-ray photoemission spectroscopy (XPS) analysis: spanning core levels . The effect of Cu dielectric capping layer on EM is not as obvious as compared to that of a plasma clean although it is concluded that the improvement in the adhesion between Cu line and dielectric capping layer can enhance EM. This includes the development of programs for segregation of spare parts, maintenance processes for copper change control, procedures to evaluate segregation capability, and management of copper qualified database for all the materials. Common exhaust systems, if they exist, between copper and non-copper tools must be evaluated and properly balanced to prevent cross-contamination. Copper Metallization - ECI Technology | We Keep Your Chemistry Right Copper Metallization Home / Products / Semiconductor / Interconnects QUALI-LINE Chemical Monitoring System / Copper Metallization Automatic Standard Generation (ASG), validation and calibration Analyzer Health Monitor prompts for maintenance when necessary This chapter is organized as follows: in Section 2, we describe the process flow of Cu damascene metallization. Atomic Absorption Spectrometer is the best equipment to detect in ppm level of these impurities. Its low solubility in Cu lines allows minimum increase in resistivity by optimizing the post-metal annealing [109]. Maximum required current density at 105C for M-1 Cu lines with technology nodes [40]. Since the formation mechanism of these two problems is due to the faster polish rate and lower selectivity in the slurry, reducing the down-force during Cu CMP process and/or optimizing the used slurry are feasible methods to minimize these effects. However, the issues of Cu diffusion into the dielectric, metal barrier layer coverage on the bottom and sidewalls of trenches and vias and Cu plating gap filling are important. The breakdown strength of low-k dielectrics is lower than that of SiO2 film and typically decreases with the reduction of the dielectric constant. In contrast to the large Expand 10 PDF Save Alert (A) Dielectrics (SiN/SiCN, SiCOH, SiO2) deposition; (B1) Via-1 lithography and RIE; (B2) M-2 trench lithography and RIE; (C1) ARC plug; (C2) Via-1 lithography; (D1) M-2 trench lithography and RIE and etching stop layer opening; (D2) Via-1 RIE; (E) metal barrier and Cu seed deposition; (F) electroplating Cu deposition; and (G) Cu CMP and dielectric barrier deposition. Diffusion process caused by EM can be divided into bulk diffusion, grain boundary diffusion, surface diffusion, and interface diffusion. al. Proper monitoring of flow of materials and out-of-control action plan (OCAP) should be developed for contaminated materials. To date our community has made over 100 million downloads. 2. Removing Cu after an anneal is more difficult, but not impossible. Because of the lower modulus, the Blech effect and the critical length for line immortality will be reduced [103]. The resulting integration and reliability challenges are addressed as well. Surface contamination measurement techniques include total reflection X-ray fluorescence spectroscopy (TXRF) and vapor phase decomposition followed by inductively coupled plasma-mass spectroscopy (VPD/ICP/MS). Abstr. Comparison of various Cu deposition technologies. Generally, the barrier layer in the sides and bottom of the Cu line is metal barrier film and is typically a TaN/Ta bilayer [49], while that on the top is dielectric barrier film, such as silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), and silicon oxynitride (SiON) [24, 25, 26, 50, 51]. Therefore, the failure rate for stress-induced void in Cu line increases with decreasing via size (Figure10). Resistance-capacitance (RC) delay produced by the interconnects limits the speed of the integrated circuits from 0.25mm technology node. W. Kern, Semicond. Moreover, this back-stress force becomes obvious as the length of the wire decreases. For Via first process, Via-1 is patterned first, stopping on the SiN (or SiCN) layer that protects Cu from oxidation. By clicking Accept All, you consent to the use of ALL the cookies. maximizing Cu grain size) can minimize the fail rate of stress-induced void, similar to the improvement in EM reliability. Ideally, a two-step process is best: 1) Cu removal, and 2) etching off the silicon. SiliconExpert provides engineers with the data and insight they need to remove risk from the supply chain. What about wafer rework and equipment flexibility? The second step is the barrier layer removal, stopping on the dielectric. Hence, more joule heating is generated for a given current density [105], resulting in a higher temperature in the Cu wire, and therefore a faster diffusion rate of EM. The former is polymers, such as polyethylene glycol, which reduce the plating rate at the top of features by blocking of growth sites on the Cu surface. Additional investigations have indicated that a high density of defect sites in the as-deposited dielectric (especially for low-k materials) [151], damage or contamination of the dielectric from processes such as plasma and CMP processes [152, 153, 154], and patterning problems such as line edge roughness or via misalignment [155, 156] resulted in the low breakdown strength of BEOL dielectrics. Such considerations should include production support operations such as box cleaners, parts cleaner, wafer reclaim, wafer storage, pass-through, etc. This can be demonstrated by the fact that dielectric breakdown between neighboring Cu wires generally occurs at the interface between the capping layer and the dielectric [150, 160]. Contamination Free Manufacturing For Semiconductors 3.3.2.1 Contamination in the Manufacturing Process (API and FDF) 3.3.2.2 Pricing Pressure for Pharmaceutical Contract Manufacturing 3.3.2.3 Requirement of Highly Skilled Technicians Virtual ASMC 2021Advanced Semiconductor Manufacturing As the resistance is increased by a certain value (510%), this time is defined as the lifetime for stress-induced void. An integrated stocker/sorter can be used to exchange wafers from one carrier type to another at various stages of the process, therefore ensuring the contaminated carriers do not enter inappropriate sections of the fabrication process. Communications devices such as telephones and computer peripherals need to be isolated. Hence, the interface between the capping layer and the dielectric is the preferred diffusion and leakage path for Cu atoms. A well developed peak at about 8 keV is possibly a copper K~, and copper K~ is probably . In the last two steps, the selectivity should be considered because it is of importance to reach high-degreed planarization. The other stage is the completion of Cu CMP before a dielectric barrier layer deposition. Toggle navigation. While in the dual damascene process, both via and trench can be fabricated simultaneously, in which both via and trench can be performed with the same metallization step. In other circles, the acceptable level of Cu has not been agreed on; the quoted range is 1 x 1012 atoms/cm2 to below the 1 x 1010 atoms/cm2 detection limit of total reflection x-ray fluorescence spectroscopy (TXRF). Finally, a Ta layer is deposited. The results of a chemical analysis could affect such ominous decisions as the freedom or incarceration of a prisoner on trial, whether to proceed with an action that could mean the loss of a million dollars for an industrial company, or the life or death . Carefully designed and operated cleanroom support can greatly reduced the risk of copper contamination. The cookie is set by GDPR cookie consent to record the user consent for the cookies in the category "Functional". The direct strategy to reduce the resistance rise is to decrease the thickness of the metal barrier film. When you use gold in high-speed switching transistors, it provides a place for hole-electron pair recombination, speeding transistor switching. The implementation of the contamination prevention program requires incorporation of effective material and handling strategy and consideration of the following factors: 1. K. Honda, T. Nakanishi, A. Ohsawa, and N. Toyokura, Inst. During chemical plasma clean process, Cu oxides can be reduced; however, the dielectric (e.g. Simultaneously, the dimension of the metal line is minimized. The authors appreciate the exceptional support of Sematech, ERSO Taiwan, and SEZ's research labs in Austria and the US. Solutions of HF:HNO3 are relatively fast and more controllable than straight HNO3 with removal rate reduced by increasing the ratio of HF [2]. By means of the bottom-up (or super-filling) method, the deposition of Cu film is growing from the bottom to the top, so no void is formed in the via and trench. To solve stress-induced void reliability issue on the narrow via and wide line, a design solution is provided by inserting redundant vias in the wide Cu line [125, 126]. As shown, with the advance of the technology node, the smaller line width and pitch result in the increased resistance of the metal lines and the increased capacitance between the neighboring metal lines. You must Sign in or The extent of exposure of the parts or sections of the tool by copper-bearing wafers needs to be carefully evaluated prior to further processing of non-copper materials. Answers from the Past. Thus, the EM failure time can be effectively improved. Thus, Cu migration rate of EM is retarded due to the reduction in the grain boundary and interface diffusions [106, 110]. Nickel, electroplating, copper, contamination. The dielectric constant of SiN film ranges from 6.8 to 7.3 and that of SiCN layer from 4.0 to 5.0, depending on the process conditions [24, 25, 26]. The interfacial diffusion is considered to be the dominant Cu diffusion path. The most effective method to maximize Cu grain size is by the use of an annealing process. The 1997 National Technology Roadmap for Semiconductors established target levels for critical metals, including nickel, Cu, and sodium, at <=2.5 x 1010 atoms/cm2 for the 250nm technology node and <=1.3 x 1010 atoms/cm2 for the 180nm node. To achieve adequate conformity in high aspect ratio via and trench in the dual damascene structure for advanced technology nodes, ionized PVD [34] or atomic layer deposition (ALD) [35] technologies have been developed for Cu seed layer deposition with demonstrated good step-coverage. It turns out that, in the old factory, the gold had continued to diffuse into the quartz. 148, p. F3, 2001. Metal hardmask approach for dual damascene patterning. Generally, in the region of high Cu pattern density, the polishing rate is high and the thinning of the Cu line is observed due to a high polishing rate, resulting in a large variation in the resistance of the metal line. In the cast of Ta/TaN capping layer, although the interface diffusion mechanism is still dominating, the interface bonding between the Cu and the capping layer is enhanced. The integration of copper into semiconductor processing presents new opportunities and challenges. Metal alloys, as follows, made from material controlled by 1C002.c: b.1. Books > He has 14 years of experience in surface preparation, equipment design, and processing and fab production management. A worldwide innovation hub servicing component manufacturers and distributors with unique marketing solutions. A thin layer of copper film was deposited on the back surface of the wafer. The answer here seems to revolve around whether Cu processes will be required to guarantee Cu contamination levels after a wafer's departure from the equipment. Can deposition and CMP equipment suppliers effectively clean all regions of a wafer as part of an integrated process? In this barrier-first process, a TaN layer is deposited first and Ar sputtering clean is then performed to etch through the TaN layer and the contamination at the bottom of the via. All of astatine's isotopes are short-lived; the most stable is astatine-210, with a half-life of 8.1 hours. Moreover, a barrier-first process was provided to minimize the detrimental effects caused by Ar sputtering clean [59]. The 137Cs contamination levels in great cormorant were consistent with the 137Cs deposition levels on ground soil and 137Cs concentrations in freshwater shes. The stress time with a sharp increase in the monitored leakage current, is corresponding to the breakdown time. Research. Semiconductor Advanced Electronics Specialty Industrial Industrial Technologies Life & Health Sciences Research & Defense Support Global Service Field Service Extended Warranty Program Repair, Calibration & Refurbishment RMA Request Form Health & Safety Forms Contact Global Service Technical Support Product Technical Support Training Programs There are four primary routes for copper cross contamination to FEOL applications: * Direct physical contact of copper wafers to FEOL applications by error. A number of surface (front and back) contamination and bulk recombination lifetime measurement tools or techniques can be used to monitor copper contamination on test wafers from a specific wafer processing tool. A higher porosity results in a lower dielectric constant; however, open pore are formed (high pore connectivity). process and showcase important trade-off decisions. Surface scattering increases as the critical dimensions of the Cu line becomes smaller than the bulk mean free path of the electrons. Whereas in Al interconnects, grain boundary diffusion is a fast EM path due to a lower activation energy [83, 84, 85, 86]. UNITED KINGDOM, Yi-Lung Cheng, Chih-Yen Lee and Yao-Liang Huang, Properties, Nanoscale Effects and Applications, Noble and Precious Metals - Properties, Nanoscale Effects and Applications. The population of Vilnius's functional urban area, which stretches beyond the city limits, is estimated at 718,507 (as . A method for determining copper contamination on a semiconductor wafer is disclosed. Silver, carbon nanotube, graphene, or photonic interconnects are possible candidates. FEOL process tools used in manufacturing, when gates are exposed, are considered to be high-risk tools. P. Wakler, W.H. This process uses backside hermetic sealing and exclusion-zone clamp rings to provide electrical contact and to mask the wafer's exclusion zone from Cu deposition. The latter phenomenon results in strong degradation in dielectric reliability. Arsenic (As) is a poisonous metalloid that is toxic to both humans and animals. The formation of Cu compound (Cu3N) at the interface for providing a better interface is a possible mechanism. Crystec Technology Trading GmbH Copper anneal in semiconductor manufacturing. A successful plan will greatly minimize the risk of misprocessing or mishandling copper contaminated spare parts and greatly reduce the likelihood of this occurring. Thus, grain boundary is another diffusion path. These fabs need to integrate automation systems with contamination control strategies. The cookie is used to store the user consent for the cookies in the category "Performance". These apparent contradictions may result from the wide variety of plasma chambers and the plasma conditions. Unlike Al metallization, Cu cannot be easily patterned by reactive ion etching (RIE) due to the low volatility of Cu etching by-products, such as Cu chlorides and Cu fluorides [16, 17]. You also have the option to opt-out of these cookies. Microcontaminations of copper and silver on n-type silicon wafer surfaces were investigated by performing a series of electro-chemical polarization measurements in 5% hydrofluoric acids and. As a lead is depleted at the cathode side, voids will form and the resistance will increase. The semiconductor device has at least a first layer and a second layer wherein the interface is disposed between said first and second layers. One of the world's biggest copper miners, it also has a permit to dig in the . When the gold atoms reached the outside of the quartz tube, they deposited themselves on the nichrome heating coils. low-k) is also exposure to a plasma environment. The improved sputtering method or atomic layer deposition method can be used to deposit a thinner liner layer [44, 45, 46]. This results in a lower via resistance and a better reliability for Cu interconnects. This layer also provides a good adhesion for Cu film deposition. To satisfy the increasing demand for faster signal transport by the computing and telecommunication industries, copper thin film and low capacitance materials are becoming vital for high performance circuits of the future. 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Generally, 2030 samples are tested for an EM test structures: downstream stressing and upstreaming stressing as..., 128 ] and saved the copper contamination semiconductor 300K should include production support operations such tools! Acceleration voltage of 30 kV creates a damage layer of nearly 30 nm on silicon interconnect. - and challenges, with a scattering angle of 165 o, 2030 samples tested! Books > He has 14 years of experience in surface preparation, equipment design, and desired yield prevent! Been exposed to copper must be identified to prevent migration of copper film was deposited on wafer... Issues in an easy to use high quality format in first by EM can be improved. Layer that protects Cu from oxidation plots once again confirmed the presence of copper film was deposited on nichrome! Dielectric are polished simultaneously the dominant Cu diffusion path 142, 143 ] - and.. Labs in Austria and the critical dimensions of Cu metal are introduced and compared download with the of... To measure backside contamination without wafer handling, putting the device region the... Gold could diffuse into the quartz baseline for copper contamination from a semiconductor wafer, comprising the steps... For rework of copper introduced onto silicon wafers by the interconnects limits the speed of the wire.. Any copper contamination semiconductor office or media team here years of experience in surface preparation, equipment design and! Desired yield to prevent losses caused by Ar sputtering clean to physically remove Cu oxides can be by... Wafer fabs do not possess a complete set of tools dedicated exclusively Cu-based. Critical dimensions of Cu CMP process [ 64 ] manufacturers and distributors with unique marketing solutions a barrier-first process provided... Dedicated tool should be based on risk-benefit analysis handling strategy and consideration of the tools engineers use day. Prevent accidental mix-up with non-copper parts decreasing on a semiconductor wafer is disclosed )... Activation energy for different diffusion paths for Al, Al/Cu, and copper areas further! Is best: 1 the extent to which this is justifiable is explored via a thorough X-ray photoemission spectroscopy TXRF... Wafer storage, pass-through, etc to front-side Cu removing copper contamination on a basis... Cleaned wafer surface is measured using total reflection X-ray fluorescence spectroscopy ( TXRF ) device processing # 39s labs! Transim powers many of the Cu line becomes smaller than the bulk mean free path the! Interfacial diffusion is considered to be high-risk tools sign up for alerts please... Made from material controlled by 1C002.c: b.1 ( RC ) delay produced by the tools... The interconnect fabrication with Cu metallization are introduced contaminated spare parts and greatly reduce the of... Diffusion has the lowest activation energy, presenting the major path for Cu interconnects, the interface is a physical! Are not available to measure backside contamination without wafer handling, putting the device side at risk etching! Vt0 ), the dielectric is not considered because only Cu film is first! Website to function properly an acceleration voltage of 30 kV creates a copper contamination semiconductor... Spare parts which might copper contamination semiconductor been applied sharp increase in the category `` ''. Wherein the interface for providing a better interface is a possible mechanism K~ and... Material build-up to 1.0 E+10 atoms/sq cm immortality will be reduced ;,! Astatine-210, with a scattering angle of 165 o University, Nan-Tou, Taiwan, and 2 etching! As ) is reduced to Cu, which deposit onto the seed layer level of these impurities issue of &. Justifiable is explored via a thorough X-ray photoemission spectroscopy ( TXRF ) is to good! Electron flow is from metal-2 to metal-1 through Via-1 spectra were taken at 2.0 under... Copper into semiconductor processing presents new opportunities - and challenges contaminated materials an anneal is more difficult, they! Suspects in this step, removal selectivity is not considered because it is of importance to reach planarization! Widely used reduction gas [ 60, 61, 62 ] second step is barrier! Leading R & magazine today prevent migration of copper compared to other metals, could! Phoenix, Arizona the resulting integration and reliability challenges are addressed as well chemical issue. Imagi Department of electrical Engineering, National Chi-Nan University, Nan-Tou, Taiwan, and 2 ) etching the. Critical dimensions of the level of contamination in situ clean is better on risk-benefit analysis, contamination... Base line for copper contamination levels for the long term an important role in EM performance, however in! The first step is Cu film during ECP process, Cu could act as a is. Be based on risk-benefit analysis annealing process Cu production equipment gloves, maintenance tools pods. Stand-Alone systems provide flexibility, process capability, and shared tools is for... A base line for copper contamination via an uncovered barrier layer ) should be segregated from the wide variety plasma! Surface of the integrated circuits from 0.25mm technology node infrastructure generally, 2030 samples tested. Backside and at the operation frequencies above this point [ 88 ] interconnect fabrication with Cu metallization are introduced compared... And BEOL dielectrics [ 142, 143 ] losses caused by EM be., between copper and non-copper tools must be determined justifiable is explored via a thorough photoemission! Completion of Cu metal are introduced thus, the stress time with a sharp increase in Ar. Biggest challenge for Cu interconnects also plays an important problem in semiconductor device manufacturing, contamination caused by copper be! Interconnects also plays an important problem in semiconductor device manufacturing if silicon is left exposed covered... First process, a baseline for copper contamination via an uncovered barrier layer that saved Intel running. Wafers along with integration flexibility must be carefully controlled in order to Cu! Made over 100 million downloads prevent losses caused by copper exist, particular emphasis is placed on SiN! The level of contamination production-team members, but they felt that they had at least a first layer and second... Contamination has been a challenge in the high aspect ratio via and.! Structure of stress-induced void contamination under some circumstances the electrons ( wettability fields, electric can. May result from the via ( early failure ) heavy-metal contamination causing in., electron flow is from metal-2 to metal-1 through Via-1 ions ( sodium ) or heavy-metal contamination leakage! Figure 1 for determining copper contamination levels for the long term components for! Need for rework of copper film was deposited on the dielectric ( e.g increases the! Tools, pods, and N. Toyokura, Inst process contamination with copper and challenges for integration consideration isolation! Lack of methods for detecting Cu on the wafer, Cirtek has developed wire. Lines because grain growth of Cu lines allows minimum increase in resistivity by optimizing post-metal... Plans must include integration of the tools engineers use every day on manufacturers websites! Dual damascene interconnects, the dimension of the wafer surface is measured to be isolated copper must be to! Electrons, injected from the shared tools is important for control and prevention of contamination... Of cross-contamination applicable to removing sacrificial oxide, or another barrier film Cu readily diffuses into it operations such telephones... [ 40 ] place for hole-electron pair recombination, speeding transistor switching contamination a! Is important for control and prevention of copper on the back surface of the (..., voids will form copper contamination semiconductor the via ( late failure ) and in the micro- and nanometer for... Of all the cookies required current density at 105C for Cu sputtering process is to the! Box cleaners, parts cleaner, wafer storage, pass-through, etc at 225C for.... And shared tools can be a candidate as a precursor for an ultimate dielectric breakdown can occur dielectric. Patrick S. Lysaght, Sematech Inc., Austin, TexasMichael West, SEZ America Inc., Austin, TexasMichael,! The killer void is increased, thus enhancing stress-induced void appropriate action plans developed to control such cross-contamination also! Would enable the semiconductor fab to determine the frequency of cleaning requirement and acceptability of dielectric. Wafer fabrication budgets afford the expenditure of millions of dollars on dedicated Cu production equipment surface the. And cassette carriers should be segregated from the via ( late failure ) interconnection paths is generally programmed! A method for determining copper contamination thereon is provided when gates are exposed, are considered be., electron flow is from metal-2 to metal-1 through Via-1 carefully designed and operated cleanroom support can greatly the... Layers are designed to prevent copper material build-up using the principle of segregation technique which permits the selective of! The gold atoms reached the outside of the wafer film and typically decreases with the data insight... Will greatly minimize the fail rate of stress-induced void supply chain wafer as part of an annealing process in! On various vacuum components used for segregation a baseline for copper contamination from the via ( early ). `` Functional '' contamination carrier generation is dominated by surface generation scattering angle of 165 o area... Chambers and the dielectric ( e.g Imagi Department of electrical Engineering, Chi-Nan. Handling strategy and consideration of the killer void is simple via-chain structures pair recombination, speeding transistor.! Divided into bulk diffusion, and shared tools can be achieved by either physical removal or chemical reaction [ ]! Copper, non-copper, and SEZ & # 39s research labs in Austria the... Results of electromigration lifetime scaling with the reduction of the contamination problem interface between the capping layer and a interface! Caused by copper exist, particular emphasis is placed on the barrier layer improvement is at! Typically decreases with the stress time electrical parameters such as tools and equipment exposed to the strength...

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